Field programmable gate arrays (FPGAs) are a rapidly evolving technology in the application-specific integrated circuit (ASIC) area. The increasing use of FPGAs in ASICs is due to the fact that they combine the flexibility of mask programmable gate arrays (MPGAs) with the convenience of field programmability.
A typical FPGA architecture consists of a two-dimensional array of logic modules or base cells that can be selectively connected using a programmable interconnect structure. The architecture includes rows of base cells interspersed with routing channels consisting of predefined tracks. The tracks are segmented and two adjacent segments can be connected by programming a horizontal antifuse.
In addition to the horizontal antifuses, there are cross-point antifuses that are used to make connections between the horizontal and the vertical tracks. FPGA architectures typically utilize a base cell that incorporates multiplexer-based logic design. The output of each base cell is connected to a dedicated vertical segment. Other vertical segments pass through the base cells serving as feed-through between channels.
The choice of architecture for base cells and the method by which the base cells are configured directly affects the usefulness and performance of an FPGA for a particular application. Performance depends mainly on the number of antifuses used and the critical path delay.
The area required for one logic implementation in comparison to another depends upon a combination of size and number of base cells required and the routing and programming resources available. A large complex base cell requires more physical area but can implement many logic functions. Thus, a smaller total number of base cells may be required for a particular design. However, the large base cells may be underutilized, resulting in wasted logic gates. On the other hand, if the base cells are too small and simple, a large number of base cells would be required to implement a complex logic function, resulting in a large interconnection requirement. Thus, there is a trade-off between the base cell size and the number of base cells required to implement a desired function.
It is desirable that the structure of a base cell be such that it can implement as many useful functions as possible using a single base cell yet require as little space as possible.